VESA DISPLAYPORT STANDARD V1.2 PDF

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VESA DisplayPort Standard. Version 1, Revision 2. January 5, Purpose. The purpose of this document is to define a flexible system and apparatus. Page 2 of Table of Reuced Bit Rate Cable-Connector Assembly Specification DisplayPort Version 1, Revision 1a January 11, 2nd The RJ PDF is a Gaussian. With the publication of DisplayPort Standard Specification Ver . DP v ( Gbps). DP va. ( Gbps). HDMI MHz Clock.


Vesa Displayport Standard V1.2 Pdf

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DisplayPort (DP) is a digital display interface developed by a consortium of PC and chip . The DisplayPort a standard can be downloaded for free from the VESA website. devices and portable media players, which includes 2-lane DisplayPort va connection. . Archived from the original (PDF) on 8 April . 07, The Video Electronics Standards Association (VESA) today formally DisplayPort v is backward compatible with existing DisplayPort va systems . VESA DisplayPort StandardVersion 1, Revision 2January 5,

This is the primary user interface clock.

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It runs as fast as MHz, which enables a screen resolution of x when using two-wide pixels. See Selecting the Pixel Interface in Chapter 3 for more information on how to select the appropriate pixel interface. This is the processor domain. The AUX clock domain is derived from this domain, but requires no additional constraints. This is the audio interface clock. The frequency will be equal to x audio sample rate.

This clock should be x audio sample rate. This clock is used by the Audio streaming interface. Table shows the clock ranges. Valid for devices which support HBR2. HBR link rate will run at MHz. Valid for Virtex-6 and Spartan-6 device families.

These registers are considered to be synchronous to the AXI4-Lite domain and asynchronous to all others. For parameters that may change while being read from the configuration space, two scenarios may exist.

VESA DisplayPort Standard, Version 1, Revision 2

In the case of single bits, the data may be read without concern as either the new value or the old value will be read as valid data. In the case of multiple bit fields, a lock bit may be used to prevent the status values from being updated while the read is occurring. For multi-bit configuration data, a toggle bit will be used indicating that the local values in the functional core should be updated. DisplayPort v Product Specification 22 Register Space Any bits not specified in Table are considered reserved and will return '0' upon read.

Main link bandwidth setting. The register uses the same values as those supported by the DPCD register of the same name in the sink device. Sets the number of lanes that will be used by the source in transmitting data. Sets the link training mode. Transmit the link quality pattern. Set to '1' when the transmitter has disabled the scrambler and transmits all symbols.

Down-spreading control.

Reads will return zeros. Enable the basic operations of the transmitter. Enable the transmission of main link video information. The values written in the register are applied at the video frame boundary only.

Enable the transmission of secondary link information. Reads from this register always return 0x0. Returns the unique identification code of the core and the current revision level. Initiates AUX channel commands of the specified length. When this bit is set to 1, the source will initiate Address only transfers STOP will be sent after the command.

The range of the register is 0 to 15 indicating between 1 and 16 bytes of data. Specifies the address for the current AUX channel command. Indicates an overflow in the user FIFO.

The event may occur if the video rate does not match the TU size programming. This bit clears upon read. Contains the raw signal values for those conditions which may cause an interrupt. Reply data is read from the FIFO starting with byte 0.

The number of bytes in the FIFO corresponds to the number of bytes requested. Reply code received from the most recent AUX Channel request.

Note: The core will not retry any commands that were Deferred or Not Acknowledged. Writing to this register clears the count. Source core interrupt status register. A read from this register clears all values.

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The duration of the pulse can be determined by reading 0x When set to a 1, the specified interrupt source is masked. This register resets to all 1s at power up. Returns the total number of data bytes actually received during a transaction. This register does not use the length byte of the transaction header.

The bit is set to '0' when the AUX transaction request controller is idle. The bit is '0' otherwise. The AUX reply controller sets this bit to '1' when a complete and valid reply transaction has been received. Specifies the total number of clocks in the horizontal framing period for the main stream video signal.

Provides the total number of lines in the main stream video frame. Provides the polarity values for the video sync signals. Sets the width of the horizontal sync pulse. Sets the width of the vertical sync pulse.

Horizontal resolution of the main stream video source. Vertical resolution of the main stream video source. Number of clocks between the leading edge of the horizontal sync and the start of active data. Number of lines between the leading edge of the vertical sync and the first line of active data.

Miscellaneous stream attributes. M value for the video stream as computed by the source core.

If synchronous clocking mode is used, this register must be written with the M value. Sets the size of a transfer unit in the framing logic On reset, transfer size is set to Note that bit 0 cannot be written the transfer unit size is always even.

N value for the video stream as computed by the source core. If synchronous clocking mode is used, this register must be written with the N value. Selects the width of the user data input port. This register is used to translate the number of pixels per line to the native internal bit datapath. Informs the DisplayPort transmitter main link that the source video is interlaced.

This bit must be set to a '1' for the proper transmission of interlaced sources. The calculation should be done based on the DisplayPort specification. This register is used to hold the fractional component. This allows enough data to be buffered in the input FIFO. Reset the transmitter PHY. Clear to release.

Set the pre-emphasis level for lane 0 of the DisplayPort link. Up to eight levels are supported for a wide variety of possible PHY implementations. The mapping of the four levels supported by the DisplayPort standard to the eight levels indicated here is implementation specific.

Controls the differential voltage swing for lane 0 of the DisplayPort link. The mapping of the four levels supported by the DisplayPort specification to the eight levels indicated here is implementation specific. Enable the pseudo random bit sequence 7 pattern transmission for link quality assessment. Control PHY Power down. One bit per lane.

When set to 1, moves the GT to power down mode. Set the pre-cursor level for lane 0 of the DisplayPort link non-spartan-6 devices. The mapping of the four levels supported by the DisplayPort standard to the 32 levels indicated here is implementation specific.

Set the post-cursor level for lane 0 of the DisplayPort link non-spartan-6 devices. Provides the current status from the PHY. The DisplayPort Audio registers are listed in Table Enables audio stream packets in main link and provides buffer control. Used to input active channel count. Transmitter collects audio samples based on this information. No protection is provided for wrong operations by software.

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M value of audio stream as computed by transmitter. N value of audio stream as computed by transmitter. Extended packet is fixed to 32 Bytes length.

The controller has buffer space for only one extended packet. This is a key-hole memory. So, nine writes to this address space is required. In the case of multiple bit fields, a lock bit may be maintained to prevent the status values from being updated while the read is occurring. Any bits not specified in Table are to be considered reserved and will return '0' upon read.

Enable the receiver 1 - Enables the receiver core. Asserts the HPD signal when set. Enables the display timing generator in the user interface.

The DTG should be disabled when the core detects the no-video pattern on the link. Configures the number of pixels output through the user data interface.

The Sink controller programs the pixel width to the active lane count default. User can override this by writing a new value to this register. Valid for designs with 2 or 4 lanes. Valid for designs with 4 lanes only. When set to a '1', the specified interrupt source is masked. Video interrupt is set after a delay of eight video frames following a valid scrambler reset character. Allows the host to instruct the receiver to pass the MSA values through unfiltered.

When set to '1', two matching values must be detected for each field of the MSA values before the associated register is updated internally. Provides a running total of errors detected on inbound AUX Channel requests.

Provides a running total of the number of AUX requests received. Instructs the receiver core to assert an interrupt to the transmitter using the HPD signal. A read from this register always returns 0x Set to '1' to send the interrupt through the HPD signal. The HPD signal is brought low for us to indicate to the source that an interrupt has been requested. Width of the recovered AUX clock from the most recent request. Provides the most recent AUX command received.

Contains the address field of the most recent AUX request. The length of the most recent AUX request is written to this register. The length of the AUX request is the value of this register plus one. Transaction lengths from 1 to 16 bytes are supported. For address only transactions, the value of this register will be 0.

Indicates the cause of a pending host interrupt. The horizontal and vertical resolution parameters are monitored for changes. The display timing generator control logic outputs a fixed length, active-high pulse for the horizontal sync.

The timing of this pulse may be controlled by setting this register appropriately. The default value of this register is 0x0f0f. Fast I2C mode clock divider value. Valid only for DPCD 1. Indicates the presence of EDID information for the video stream.

Indicates the presence of EDID information for the audio stream. General byte for passing remote information to the transmitter. A write of 0x0 to this register has no effect. Refer to DPCD register section of the specification for more details. Reads from this register reflect the state of DPCD register.

DPCD register bit to inform the transmitter that video data is not supported. DPCD register bit to inform the transmitter that audio data is not supported 0 - Set to '1' when audio data is not supported. Reserved for v1. Allows the user to setup GUID if required from host interface. DisplayPort 1. It also has the ability to share this bandwidth with multiple streams of audio and video to separate devices. However, they predicted that the figure for commercial desktops would grow to Shortly after announcing Mini DisplayPort, Apple announced that it would license the connector technology with no fee.

This new standard will be physically smaller than the currently available mini DisplayPort connectors. The standard was expected to be released by Q2 It allows for controller-less monitors where the display panel is directly driven by the DisplayPort signal, although the available resolutions and color depth are limited to two-lane operation.

DSC 1. It aims to define a standardized display panel interface for internal connections; e. Version 1. The iDP standard defines an internal link between a digital TV system on a chip controller and the display panel's timing controller.

SlimPort implements the transmission of video up to 4K-UltraHD and up to eight channels of audio over the micro-USB connector to an external converter accessory or display device.

VESA ratifies DisplayPort 1.4 standard

DisplayID features variable-length structures which encompass all existing EDID extensions as well as new extensions for 3D displays and embedded displays. The latest version 1.Using horizontal and vertical sync signals for framing, this user interface matches the industry standard for display controllers and plugs in to existing video streams with little effort. IP also comes with example design and test bench. Top of this page NaViSet Administrator 2 This software is an all-in-one remote support solution that runs from a cent ral locat ion and provides monitoring, asset management and control functionality of the majority of NEC display devices and Windows computers.

Total number of active video lines in a frame of video. DSC 1. The length of the most recent AUX request is written to this register.

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